Exception Control
FROM RESET
BREAK
I BIT SET?
YES
INTERRUPT?
NO
YES
I-BIT SET?
NO
IRQ1
INTERRUPT?
YES
NO
STACK CPU REGISTERS
SET I-BIT
LOAD PC WITH INTERRUPT VECTOR
AS MANY INTERRUPTS
AS EXIST ON CHIP
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
INSTRUCTION?
NO
Figure 7-10. Interrupt Processing
7.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt
is serviced first. Figure 7-11 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
105
FREESCALE [ Freescale ]
