Freescale Semiconductor, Inc.
Interrupts
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
•
•
•
•
UNSTACKING
ORDER
•
•
5
4
3
2
1
1
2
3
4
5
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
STACKING
ORDER
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-4. Interrupt Stacking Order
NOTE: If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit. See Table 4-1 for a priority
listing.
Figure 4-5 shows the sequence of events caused by an interrupt.
Technical Data
58
MC68HC705C8A — Rev. 3
Interrupts
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