Freescale Semiconductor, Inc.
Memory
Addr.
Register Name
Bit 7
SPIE
0
6
5
4
3
CPOL
U
2
CPHA
U
1
SPR1
U
Bit 0
SPR0
U
Read:
SPI Control Register
SPE
MSTR
$000A
(SPCR) Write:
See page 149.
Reset:
0
0
Read: SPIF
WCOL
MODF
SPI Status Register
(SPSR) Write:
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
See page 151.
Reset:
Read:
0
0
0
SPI Data Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BIt 2
Bit 1
Bit 0
(SPDR) Write:
See page 149.
Reset:
Read:
Unaffected by reset
SCP0
Baud Rate Register
SCP1
0
SCR2
U
SCR1
U
SCR0
U
(Baud) Write:
See page 136.
Reset:
Read:
U
R8
U
U
T8
0
M
U
WAKE
U
SCI Control Register 1
(SCCR1) Write:
See page 130.
Reset:
Read:
U
U
SCI Control Register 2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
(SCCR2) Write:
See page 131.
Reset:
0
0
0
0
0
0
0
Read: TDRE
TC
RDRF
IDLE
OR
NF
FE
SCI Status Register
(SCSR) Write:
See page 133.
Reset:
Read:
1
1
0
0
0
0
0
U
SCI Data Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(SCDR) Write:
See page 129.
Reset:
Read:
Unaffected by reset
Timer Control Register
ICIE
0
OCIE
0
TOIE
0
0
0
0
0
0
IEDG
U
OLVL
0
(TCR) Write:
See page 94.
Reset:
0
= Unimplemented
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 2 of 4)
Technical Data
40
MC68HC705C8A — Rev. 3
Memory
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