Freescale Semiconductor, Inc.
General Description
Block Diagram
PA0
PA1
PA2
EPROM PROGRAMMING
CONTROL
PROGRAM REGISTER
V
PP
N
ITO
A
C
PA3
T
PA4
P
D
EPROM/OTPROM — 7744 BYTES
(144 BYTES CONFIGURABLE)
A
PA5
PA6
PA7
A
OPTION
REGISTER
PB0*
PB1*
PB2*
PB3*
PB4*
PB5*
PB6*
PB7*
B
RAM — 176 BYTES
(304 BYTES MAXIMUM)
B
C
BOOT ROM — 240 BYTES
RESET
IRQ
ARITHMETIC
LOGIC UNIT
CPU
CONTROL
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7†
M68HC05 CPU
CPU REGISTERS
ACCUMULATOR
INDEX REGISTER
1
STACK POINTER
0
0
0
0
0
1
PROGRAM COUNTER
PD7
1
1
1
H
I
N Z C
CONDITION CODE REGISTER
RDI (PD0)
TDO (PD1)
MISO (PD2)
MOSI (PD3)
SCK (PD4)
SS (PD5)
SCI
SPI
OSC2
OSC1
INTERNAL
PROCESSOR
CLOCK
÷ 2
OSCILLATOR
COP WATCHDOG
AND
CLOCK MONITOR
BAUD RATE
GENERATOR
V
DD
TCMP
TCAP
POWER
16-BIT
CAPTURE/COMPARE
TIMER SYSTEM
V
SS
* Port B pins also function as external interrupts.
† PC7 has a high current sink and source capability.
Figure 1-2. MC68HC705C8A Block Diagram
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
General Description
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