Freescale Semiconductor, Inc.
Ele c tric a l Sp e c ific a tions
13.8 3.3-Volt DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
V
V
—
—
—
0.1
—
OL
Output voltage, I
≤ 10.0 µA
V
Load
V
V
– 0.1
DD
OH
Output high voltage
I
= –0.2 mA
Load
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(see Figure 13-2)
—
—
—
—
—
—
V
– 0.3
V
OH
DD
I
I
= –0.4 mA
Load
PD4–PD1 (see Figure 13-3)
= –1.5 mA
Load
PC7
Output low voltage (see Figure 13-4)
I
I
= 0.4 mA
Load
V
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
= 6.0 mA
—
—
—
0.3
0.3
V
V
OL
Load
—
PC7
Input high voltage
V
0.7 x V
V
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0,
PD7, TCAP, IRQ, RESET, OSC1
—
IH
DD
DD
Input low voltage
V
V
0.2 x V
—
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0,
PD7, TCAP, IRQ, RESET, OSCI
—
—
V
V
IL
SS
DD
V
Data-retention mode (0°C to 70°C)
2.0
RM
(3)
Supply current
(4)
Run
—
—
—
1.53
0.711
2.0
3.0
1.0
20
mA
mA
µA
I
DD
(5)
Wait
(6)
Stop
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0, PC7–PC0, PD4–PD1,
PD7, RESET
I
I
—
—
—
—
± 10
± 1
µA
µA
IL
In
Input current
IRQ, TCAP, OSC1, PD5, PD0
1. V = 3.3 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
2. Typical values at midpoint of voltage range, 25°C only.
3. I measured with port B pullup devices disabled.
DD
4. Run (operating) I measured using external square wave clock source (f
= 2.0 MHz). All inputs 0.2 V from rail. No dc
DD
OSC
loads. Less than 50 pF on all outputs. C = 20 pF on OSC2. OSC2 capacitance linearly affects run I
L
DD.
5. Wait I measured using external square wave clock source (f
= 2.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
DD
OSC
than 50 pF on all outputs. C = 20 pF on OSC2. V = 0.2 V, V = V – 0.2 V. All ports configured as inputs. SPI and SCI
L
IL
IH
DD
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait I
.
DD
6. Stop I measured with OSC1 = V . All ports configured as inputs. V = 0.2 V; V = V – 0.2 V.
DD
DD
IL
IH
DD
Technical Data
176
MC68HC705C8A — Rev. 3
Electrical Specifications
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