Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
SCI I/O Registers
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
10.6.4 SCI Status Register
The SCI status register (SCSR) shown in Figure 10-8 contains flags to
signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
Address: $0010
Bit 7
Read: TDRE
Write:
6
5
4
3
2
1
Bit 0
U
TC
RDRF
IDLE
OR
NF
FE
Reset:
1
1
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 10-8. SCI Status Register (SCSR)
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
