Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
SCI I/O Registers
• Framing Errors — If the data recovery logic does not detect a logic
1 where the stop bit should be in an incoming character, it sets the
framing error (FE) bit in the SCSR. The FE bit is set at the same
time that the RDRF bit is set.
• Receiver Interrupts — These sources can generate SCI receiver
interrupt requests:
– Receive Data Register Full (RDRF) — The RDRF bit in the
SCSR indicates that the receive shift register has transferred a
character to the SCDR.
– Receiver Overrun (OR) — The OR bit in the SCSR indicates
that the receive shift register shifted in a new character before
the previous character was read from the SCDR.
– Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10
or 11 consecutive logic 1s shifted in from the PD0/RDI pin.
10.6 SCI I/O Registers
These I/O registers control and monitor SCI operation:
• SCI data register (SCDR)
• SCI control register 1 (SCCR1)
• SCI control register 2 (SCCR2)
• SCI status register (SCSR)
10.6.1 SCI Data Register
The SCI data register (SCDR) shown in Figure 10-5 is the buffer for
characters received and for characters transmitted.
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Unaffected by reset
Figure 10-5. SCI Data Register (SCDR)
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Serial Communications Interface (SCI)
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