Freescale Semiconductor, Inc.
EPROM/OTPROM (PROM)
Control Registers
SEC — Security Bit
This bit is implemented as an EPROM cell and is not affected by
reset.
1 = Security enabled
0 = Security off; bootloader able to be enabled
IRQ — Interrupt Request Pin Sensitivity Bit
IRQ is set only by reset, but can be cleared by software. This bit can
only be written once.
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
9.5.2 Mask Option Register 1
Mask option register 1 (MOR1) shown in Figure 9-5 is an EPROM
register that enables the port B pullup devices. Data from MOR1 is
latched on the rising edge of the voltage on the RESET pin.
See 4.3.3 Port B Interrupts.
Address: $1FF0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
PBPU0/
COPC
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
Reset:
Erased:
Unaffected by reset
0
0
0
0
0
0
0
0
Figure 9-5. Mask Option Register 1 (MOR1)
PBPU7–PBPU0/COPC — Port B Pullup Enable Bits 7–0
These EPROM bits enable the port B pullup devices.
1 = Port B pullups enabled
0 = Port B pullups disabled
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
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