I/O Section
$FF81
↓
RESERVED (7 BYTES)
$FF87
$FF88
$FF89
↓
$FF8F
$FF90
↓
$FFBF
$FFC0
↓
$FFCB
$FFCC
↓
$FFFF
VECTORS (52 BYTES)
See
RESERVED (12 BYTES)
UNIMPLEMENTED (48 BYTES)
RESERVED (7 BYTES)
FLASH CONTROL REGISTER (FLCR)
Figure 2-1. Memory Map (Sheet 3 of 3)
2.2 I/O Section
Addresses $0000–$004F, shown in
contain the I/O Data, Status and Control Registers.
Addr.
$0000
Register Name
Port A Data Register Read:
(PTA) Write:
Port B Data Register Read:
(PTB) Write:
Port C Data Register Read:
(PTC) Write:
Port D Data Register Read:
(PTD) Write:
Data Direction Register A Read:
(DDRA) Write:
Data Direction Register B Read:
(DDRB) Write:
Bit 7
PTA7
6
PTA6
5
PTA5
4
PTA4
3
PTA3
2
PTA2
1
PTA1
Bit 0
PTA0
$0001
PTB7
0
R
PTD7
PTB6
0
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
$0002
PTC5
R
PTD6
PTD5
PTC4
PTC3
PTC2
PTC1
PTC0
$0003
PTD4
PTD3
PTD2
PTD1
PTD0
$0004
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
$0005
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
= Unimplemented
R
= Reserved
Figure 2-2. I/O Data, Status and Control Registers (Sheet 1 of 6)
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
31
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
