Freescale Semiconductor, Inc.
List of Figures
Figure
Title
Page
22-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .385
22-4 Timer A Status and Control Register (TASC). . . . . . . . . . . . .393
22-5 TIMA Counter Registers (TCNTH and TCNTL) . . . . . . . . . . .395
22-6 TIMA Counter Modulo Registers
(TAMODH and TAMODL) . . . . . . . . . . . . . . . . . . . . . . . . .396
22-7 TIMA Channel Status
and Control Registers (TACC0–TASC5) . . . . . . . . . . . . . .397
22-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
22-9 TIMA Channel Registers (TACH0H/L–TACH3H/L) . . . . . . . .403
23-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
23-2 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .413
23-3 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . .416
23-4 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .416
24-1 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .426
24-2 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .427
24-3 BDLC Variable Pulse-Width Modulation (VPW)
Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432
Technical Data
MC68HC908AS60 — Rev. 1.0
List of Figures
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