Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
SCI During Break Module Interrupts
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
17.7 SCI During Break Module Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Section 12. Break
Module.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
17.8 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
1. PTE0/SCTxD — Transmit data
2. PTE1/SCRxD — Receive data
17.8.1 PTE0/SCTxD (Transmit Data)
The PTE0/SCTxD pin is the serial data output from the SCI transmitter.
The SCI shares the PTE0/SCTxD pin with port E. When the SCI is
enabled, the PTE0/SCTxD pin is an output regardless of the state of the
DDRE2 bit in data direction register E (DDRE).
MC68HC908AS60 — Rev. 1.0
Technical Data
Serial Communications Interface (SCI)
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