Freescale Semiconductor, Inc.
System Integration Module (SIM)
9.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .151
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .153
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .154
9.8.1
9.8.2
9.8.3
9.2 Introduction
This section describes the system integration module (SIM), which
supports up to 32 external and/or internal interrupts. Together with the
central processor unit (CPU), the SIM controls all MCU activities. The
SIM is a system state controller that coordinates CPU and exception
timing. A block diagram of the SIM is shown in Figure 9-1. Figure 9-2 is
a summary of the SIM input/output (I/O) registers.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Technical Data
MC68HC908AS60 — Rev. 1.0
System Integration Module (SIM)
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