Monitor ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: MMRD7
MMRD6
MMRD5
MMRD4
MMRD3
MMRD2
MMRD1
MMRD0
MMIIC Data Receive
$004D
Register Write:
(MMDRR)
Reset:
0
0
0
0
0
0
0
0
Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0
Write:
MMIIC CRC Data Register
(MMCRDR)
$004E
$004F
$0050
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
$0059
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
0
0
0
MMIIC Frequency Divider
MMBR2
MMBR1
MMBR0
Register Write:
(MMFDR)
Reset:
0
0
0
0
0
1
0
0
Read:
Reserved Write:
Reset:
R
R
R
R
R
R
R
R
Read:
TBIF
0
0
TACK
0
Timebase Control Register
TBR2
0
TBR1
0
TBR0
0
TBIE
0
TBON
0
R
0
(TBCR) Write:
Reset:
Read:
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
Read:
COCO
ADC Status and Control
AIEN
0
ADCO
0
ADCH4
1
ADCH3
1
ADCH2
1
ADCH1
ADCH0
Register Write:
(ADSCR)
Reset:
0
1
0
1
0
Read:
ADIV2
ADIV1
ADIV0
ADICLK
MODE1
MODE0
ADC Clock Control Register
(ADICLK)
Write:
Reset:
Read:
Write:
Reset:
R
0
ADx
R
0
ADx
R
0
ADx
R
0
ADx
R
0
ADx
R
0
ADx
R
0
0
ADx
ADx
R
ADC Data Register High 0
(ADRH0)
R
0
0
0
0
0
0
0
0
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9)
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
37
FREESCALE [ Freescale ]
