Memory
Addr.
Register Name
Timer 1 Channel 0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
$0026
$0027
Register High Write:
(T1CH0H)
Reset:
Indeterminate after reset
Read:
Timer 1 Channel 0
Bit 7
6
5
0
4
3
2
1
Bit 0
Register Low Write:
(T1CH0L)
Reset:
Indeterminate after reset
Read:
Write:
CH1F
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
Timer 1 Channel 1 Status and
Control Register (T1SC1)
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
0
0
Reset:
Read:
0
0
0
0
0
9
0
Timer 1 Channel 1
Bit 15
14
13
12
11
10
Bit 8
Register High Write:
(T1CH1H)
Reset:
Indeterminate after reset
Read:
Timer 1 Channel 1
Bit 7
6
5
4
3
2
1
Bit 0
PS0
Register Low Write:
(T1CH1L)
Reset:
Indeterminate after reset
Read:
TOF
0
0
TRST
0
0
Timer 2 Status and
Control Register Write:
TOIE
TSTOP
PS2
PS1
(T2SC)
Reset:
0
0
1
0
0
0
9
0
Read:
Bit 15
14
13
12
11
10
Bit 8
Timer 2 Counter
Register High Write:
(T2CNTH)
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Read:
Bit 7
Bit 0
Timer 2 Counter
Register Low Write:
(T2CNTL)
Reset:
0
Bit 15
1
0
0
0
0
0
0
0
Read:
Timer 2 Counter Modulo Reg-
14
13
12
11
10
9
Bit 8
ister High Write:
(T2MODH)
Reset:
1
1
1
1
1
1
1
Bit 0
1
Read:
Timer 2 Counter Modulo
Bit 7
6
1
5
1
4
1
3
2
1
Register Low Write:
(T2MODL)
Reset:
1
CH0F
0
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
Read:
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
Timer 2 Channel 0 Status and
Control Register (T2SC0)
Write:
Reset:
Read:
0
Timer 2 Channel 0
Bit 15
Bit 7
14
13
12
11
10
9
Bit 8
Register High Write:
(T2CH0H)
Reset:
Indeterminate after reset
Read:
Timer 2 Channel 0
6
5
4
3
2
1
Bit 0
Register Low Write:
(T2CH0L)
Reset:
Indeterminate after reset
= Unimplemented
U = Unaffected
X = Indeterminate
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9)
MC68HC908AP Family Data Sheet, Rev. 4
34
Freescale Semiconductor
FREESCALE [ Freescale ]
