Monitor ROM
Addr.
Register Name
Bit 7
CH1F
0
6
CH1IE
0
5
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
Bit 0
Read:
Write:
Reset:
Read:
0
TOV1
CH1MAX
Timer 2 Channel 1 Status and
Control Register (T2SC1)
$0033
0
0
0
9
0
Timer 2 Channel 1
Bit 15
Bit 7
14
13
12
11
10
Bit 8
$0034
$0035
Register High Write:
(T2CH1H)
Reset:
Indeterminate after reset
Read:
Timer 2 Channel 1
6
5
4
3
2
1
Bit 0
Register Low Write:
(T2CH1L)
Reset:
Indeterminate after reset
Read:
PLLF
PLLIE
0
PLLON
1
BCS
PRE1
PRE0
VPR1
VPR0
$0036 PLL Control Register (PCTL) Write:
Reset:
0
0
0
0
0
0
0
0
0
0
Read:
LOCK
PLL Bandwidth Control Reg-
AUTO
ACQ
R
$0037
$0038
$0039
$003A
$003B
$003C
$003D
$003E
$003F
ister Write:
(PBWC)
Reset:
Read:
0
0
0
0
0
0
0
0
0
MUL11
0
0
MUL10
0
0
MUL9
0
0
MUL8
0
PLL Multiplier Select
Register High Write:
(PMSH)
Reset:
0
0
0
0
Read:
PLL Multiplier Select
MUL7
0
MUL6
1
MUL5
0
MUL4
0
MUL3
0
MUL2
0
MUL1
0
MUL0
0
Register Low Write:
(PMSL)
Reset:
Read:
PLL VCO Range Select
VRS7
VRS6
VRS5
VRS4
VRS3
0
VRS2
0
VRS1
0
VRS0
0
Register Write:
(PMRS)
Reset:
0
0
1
0
0
0
0
0
Read:
PLL Reference Divider
RDS3
0
RDS2
0
RDS1
0
RDS0
1
Select Register Write:
(PMDS)
Reset:
0
0
0
0
Read:
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
35
FREESCALE [ Freescale ]
