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MC68HC908AP64CFB 参数 Datasheet PDF下载

MC68HC908AP64CFB图片预览
型号: MC68HC908AP64CFB
PDF下载: 下载PDF文件 查看货源
内容描述: [MC68HC908AP64CFB]
分类和应用: 外围集成电路时钟
文件页数/大小: 325 页 / 1651 K
品牌: FREESCALE [ Freescale ]
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I/O Registers  
12.9.4 IRSCI Status Register 1  
SCI status register 1 contains flags to signal these conditions:  
Transfer of IRSCDR data to transmit shift register complete  
Transmission complete  
Transfer of receive shift register data to IRSCDR complete  
Receiver input idle  
Receiver overrun  
Noisy data  
Framing error  
Parity error  
Address:  
$0043  
Bit 7  
6
5
4
3
2
1
Bit 0  
PE  
Read:  
Write:  
Reset:  
SCTE  
TC  
SCRF  
IDLE  
OR  
NF  
FE  
1
1
0
0
0
0
0
0
= Unimplemented  
Figure 12-15. IRSCI Status Register 1 (IRSCS1)  
SCTE — SCI Transmitter Empty Bit  
This clearable, read-only bit is set when the IRSCDR transfers a character to the transmit shift register.  
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in IRSCC2 is set,  
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by  
reading IRSCS1 with SCTE set and then writing to IRSCDR. Reset sets the SCTE bit.  
1 = IRSCDR data transferred to transmit shift register  
0 = IRSCDR data not transferred to transmit shift register  
TC — Transmission Complete Bit  
This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being  
transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in IRSCC2 is also  
set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There  
may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the  
transmission actually starting. Reset sets the TC bit.  
1 = No transmission in progress  
0 = Transmission in progress  
SCRF — SCI Receiver Full Bit  
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data  
register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in IRSCC2  
is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading  
IRSCS1 with SCRF set and then reading the IRSCDR. Reset clears SCRF.  
1 = Received data available in IRSCDR  
0 = Data not available in IRSCDR  
IDLE — Receiver Idle Bit  
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.  
IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in IRSCC2 is also set. Clear the  
IDLE bit by reading IRSCS1 with IDLE set and then reading the IRSCDR. After the receiver is enabled,  
MC68HC908AP Family Data Sheet, Rev. 4  
Freescale Semiconductor  
203  
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