Serial Communications Interface Module (SCI)
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most
significant bit position of a received character or an idle condition on the RxD pin. Reset clears the
WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The
counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then
a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning
the count after the stop bit avoids false idle character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 11-5.) When enabled, the parity function
inserts a parity bit in the most significant bit position. (See Figure 11-3.) Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See Table 11-5.) Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 11-5. Character Format Selection
Control Bits
PEN:PTY
Character Format
Start
Bits
Data
Bits
Stop
Character
Length
M
Parity
Bits
0
1
0
0
1
1
0X
0X
10
11
10
11
1
1
1
1
1
1
8
9
7
7
8
8
None
None
Even
Odd
1
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
1
1
1
Even
Odd
1
1
MC68HC908AP Family Data Sheet, Rev. 4
170
Freescale Semiconductor
FREESCALE [ Freescale ]
