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MC68HC908AP64CFB 参数 Datasheet PDF下载

MC68HC908AP64CFB图片预览
型号: MC68HC908AP64CFB
PDF下载: 下载PDF文件 查看货源
内容描述: [MC68HC908AP64CFB]
分类和应用: 外围集成电路时钟
文件页数/大小: 325 页 / 1651 K
品牌: FREESCALE [ Freescale ]
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Functional Description  
Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit  
verification is not successful, the RT clock is reset and a new search for a start bit begins.  
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and  
RT10. Table 11-3 summarizes the results of the data bit samples.  
Table 11-3. Data Bit Recovery  
RT8, RT9, and RT10  
Samples  
Data Bit  
Determination  
Noise Flag  
000  
001  
010  
011  
100  
101  
110  
111  
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
NOTE  
The RT8, RT9, and RT10 samples do not affect start bit verification. If any  
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a  
successful start bit verification, the noise flag (NF) is set and the receiver  
assumes that the bit is a start bit.  
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 11-4  
summarizes the results of the stop bit samples.  
Table 11-4. Stop Bit Recovery  
RT8, RT9, and RT10  
Samples  
Framing  
Error Flag  
Noise Flag  
000  
001  
010  
011  
100  
101  
110  
111  
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
MC68HC908AP Family Data Sheet, Rev. 4  
Freescale Semiconductor  
163  
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