Functional Description
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the
SCRF bit generates a receiver CPU interrupt request.
INTERNAL BUS
SCIBDSRC
FROM
CONFIG2
SCR1
SCR2
SCR0
SCP1
SCP0
SCI DATA REGISTER
SL
A
B
CGMXCLK
BUS CLOCK
PRE- BAUD
SCALER DIVIDER
X
÷ 4
÷ 16
11-BIT
RECEIVE SHIFT REGISTER
SL = 0 => X = A
SL = 1 => X = B
DATA
RECOVERY
H
8
7
6
5
4
3
2
1
0
L
RxD
ALL 0s
BKF
RPF
M
RWU
SCRF
IDLE
WAKE
ILTY
WAKEUP
LOGIC
PEN
PTY
R8
PARITY
CHECKING
IDLE
ILIE
ILIE
DMARE
SCRF
SCRIE
DMARE
SCRIE
SCRF
SCRIE
DMARE
DMARE
OR
OR
ORIE
ORIE
NF
NF
NEIE
NEIE
FE
FE
FEIE
FEIE
PE
PE
PEIE
PEIE
Figure 11-5. SCI Receiver Block Diagram
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
161
FREESCALE [ Freescale ]
