Timer Interface Module (TIM)
Addr.
Register Name
TIM2 Counter Modulo
Register Low
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
1
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
6
1
5
1
4
1
3
2
1
$002F
1
CH0F
0
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
(T2MODL)
TIM2 Channel 0 Status
and Control Register
(T2SC0)
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
$0030
$0031
$0032
$0033
$0034
$0035
0
TIM2 Channel 0
Register High
(T2CH0H)
Bit 15
Bit 7
14
13
12
11
10
9
Bit 8
Indeterminate after reset
TIM2 Channel 0
Register Low
(T2CH0L)
6
5
0
4
3
2
1
Bit 0
Indeterminate after reset
CH1F
TIM2 Channel 1 Status
and Control Register
(T2SC1)
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
9
0
TIM2 Channel 1
Register High
(T2CH1H)
Bit 15
14
13
12
11
10
Bit 8
Indeterminate after reset
TIM2 Channel 1
Register Low
(T2CH1L)
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset
= Unimplemented
Figure 9-2. TIM I/O Register Summary (Sheet 2 of 2)
9.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
9.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
9.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
9.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 9.4.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
MC68HC908AP Family Data Sheet, Rev. 4
138
Freescale Semiconductor
FREESCALE [ Freescale ]
