Chapter 9
Timer Interface Module (TIM)
9.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a
timing reference with Input capture, output compare, and pulse-width-modulation functions. Figure 9-1 is
a block diagram of the TIM.
This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
9.2 Features
Features of the TIM include:
•
Two input capture/output compare channels:
–
–
Rising-edge, falling-edge, or any-edge input capture trigger
Set, clear, or toggle output compare action
•
•
•
•
•
Buffered and unbuffered pulse-width-modulation (PWM) signal generation
Programmable TIM clock input with 7-frequency internal bus clock prescaler selection
Free-running or modulo up-count operation
Toggle any channel pin on overflow
TIM counter stop and reset bits
9.3 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are
T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where “1” is used to indicate TIM1 and “2”
is used to indicate TIM2. The two TIMs share four I/O pins with four I/O port pins. The external clock input
for TIM2 is shared with the an ADC channel pin. The full names of the TIM I/O pins are listed in Table 9-1.
The generic pin names appear in the text that follows.
Table 9-1. Pin Name Conventions
TIM Generic Pin Names:
T[1,2]CH0
PTB4/T1CH0
PTB6/T2CH0
T[1,2]CH1
PTB5/T1CH1
PTB7/T2CH1
TIM1
Full TIM
Pin Names:
TIM2
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TCH0 may refer generically to
T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
135
FREESCALE [ Freescale ]
