Functional Description
Addr.
Register Name
TIM1 Status and Control
Register
Bit 7
TOF
0
6
5
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
TOIE
TSTOP
PS2
PS1
PS0
TRST
0
$0020
0
0
1
0
0
0
9
0
(T1SC)
Bit 15
14
13
12
11
10
Bit 8
TIM1 Counter Register
High
(T1CNTH)
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
TIM1 Counter Register
Low
(T1CNTL)
0
Bit 15
1
0
0
0
0
0
0
0
TIM Counter Modulo
Register High
(TMODH)
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
Bit 0
1
TIM1 Counter Modulo
Register Low
(T1MODL)
Bit 7
6
1
5
1
4
1
3
2
1
1
CH0F
0
1
ELS0B
0
1
ELS0A
0
1
TOV0
0
TIM1 Channel 0 Status
and Control Register
(T1SC0)
CH0IE
0
MS0B
0
MS0A
0
CH0MAX
0
0
TIM1 Channel 0
Register High
(T1CH0H)
Bit 15
Bit 7
14
13
12
11
10
9
Bit 8
Indeterminate after reset
TIM1 Channel 0
Register Low
(T1CH0L)
6
5
0
4
3
2
1
Bit 0
Indeterminate after reset
CH1F
TIM1 Channel 1 Status
and Control Register
(T1SC1)
CH1IE
MS1A
0
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
9
0
TIM1 Channel 1
Register High
(T1CH1H)
Bit 15
14
13
12
11
10
Bit 8
Indeterminate after reset
TIM1 Channel 1
Register Low
(T1CH1L)
Bit 7
6
5
4
3
2
1
Bit 0
PS0
Indeterminate after reset
TOF
0
0
TRST
0
0
TIM2 Status and Control
Register
(T2SC)
TOIE
TSTOP
PS2
PS1
0
0
1
0
0
0
9
0
Bit 15
14
13
12
11
10
Bit 8
TIM2 Counter Register
High
(T2CNTH)
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
TIM2 Counter Register
Low
(T2CNTL)
0
Bit 15
1
0
14
1
0
13
1
0
12
1
0
11
1
0
10
1
0
9
1
0
Bit 8
1
TIM2 Counter Modulo
Register High
(T2MODH)
= Unimplemented
Figure 9-2. TIM I/O Register Summary (Sheet 1 of 2)
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
137
FREESCALE [ Freescale ]
