Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
5.8.5 SCSR2 — SCI status register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCI 1 status 2 (SCSR2)
$0075 RAF 0000 0000
0
0
0
0
0
0
0
In the SCSR2 only bit 0 is used, to indicate receiver active. The other
seven bits always read zero.
Bits [7:1] — Not implemented; always read zero
RAF — Receiver active flag (read only)
1 = A character is being received.
0 = A character is not being received.
5.8.6 SCDRH, SCDRL — SCI data high/low registers
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
$0076 R8 T8
SCI 1 data high (SCDRH)
SCI 1 data low (SCDRL)
0
0
0
0
0
0
undefined
$0077 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 undefined
SCDRH/SCDRL is a parallel register that performs two functions. It is the
receive data register when it is read, and the transmit data register when
it is written. Reads access the receive data buffer and writes access the
transmit data buffer. Data received or transmitted is double buffered.
R8 — Receiver bit 8
Ninth serial data bit received when SCI is configured for a nine data
bit operation
T8 — Transmitter bit 8
Ninth serial data bit transmitted when SCI is configured for a nine data
bit operation
Bits [5:0] — Not implemented; always read zero
R/T[7:0] — Receiver/transmitter data bits [7:0]
SCI data is double buffered in both directions.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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