Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
5.8.4 SCSR1 — SCI status register 1
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
$0074 TDRE TC RDRF IDLE OR NF FE
SCI 1 status 1 (SCSR1)
PF 1100 0000
The bits in SCSR1 indicate certain conditions in the SCI hardware and
are automatically cleared by special acknowledge sequences.
TDRE — Transmit data register empty flag
1 = SCDR empty.
0 = SCDR busy.
This flag is set when SCDR is empty. Clear the TDRE flag by reading
SCSR1 with TDRE set and then writing to SCDR.
TC — Transmit complete flag
1 = Transmitter idle.
0 = Transmitter busy.
This flag is set when the transmitter is idle (no data, preamble, or
break transmission in progress). Clear the TC flag by reading SCSR1
with TC set and then writing to SCDR.
RDRF — Receive data register full flag
1 = SCDR full.
0 = SCDR empty.
Once cleared, IDLE is not set again until the RXD line has been active
and becomes idle again. RDRF is set if a received character is ready
to be read from SCDR. Clear the RDRF flag by reading SCSR1 with
RDRF set and then reading SCDR.
IDLE — Idle line detected flag
1 = RXD line is idle.
0 = RXD line is active.
This flag is set if the RXD line is idle. Once cleared, IDLE is not set
again until the RXD line has been active and becomes idle again. The
IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR1
with IDLE set and then reading SCDR.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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