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MC33989DW 参数 Datasheet PDF下载

MC33989DW图片预览
型号: MC33989DW
PDF下载: 下载PDF文件 查看货源
内容描述: 系统基础芯片,高速CAN收发器 [System Basis Chip with High-Speed CAN Transceiver]
分类和应用: 电信集成电路光电二极管
文件页数/大小: 66 页 / 2154 K
品牌: FREESCALE [ Freescale ]
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ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. Dynamic Electrical Characteristics (continued)  
Characteristics noted under conditions 7.0 V VSUP 18 V, -40°C TA 125°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
NR  
Min  
Typ  
Max  
Unit  
Normal Request Mode Timeout  
Normal Request Modes  
ms  
TOUT  
1STOP  
2STOP  
3STOP  
4STOP  
2ACC  
308  
6.82  
31.5  
70  
350  
9.75  
45  
392  
12.7  
58.5  
130  
455  
30  
Watchdog Period 1 - Stop  
Stop Mode  
WD  
WD  
WD  
WD  
ms  
ms  
ms  
ms  
%
Watchdog Period 2 - Stop  
Stop Mode  
Watchdog Period 3 - Stop  
Stop Mode  
100  
350  
Watchdog Period 4 - Stop  
Stop Mode  
245  
-30  
Stop Mode Watchdog Period Accuracy  
Stop Mode  
f
Cyclic Sense/FWU Timing 1  
Sleep and Stop Modes  
CS  
CS  
CS  
CS  
CS  
CS  
CS  
CS  
t
ms  
ms  
ms  
ms  
ms  
ms  
ms  
ms  
µs  
FWU1  
FWU2  
FWU3  
FWU4  
FWU5  
FWU6  
FWU7  
FWU8  
ON  
3.22  
6.47  
12.9  
25.9  
51.8  
66.8  
134  
271  
200  
4.6  
5.98  
12  
Cyclic Sense/FWU Timing 2  
Sleep and Stop Modes  
9.25  
18.5  
37  
Cyclic Sense/FWU Timing 3  
Sleep and Stop Modes  
24  
Cyclic Sense/FWU Timing 4  
Sleep and Stop Modes  
48.1  
96.2  
124  
248  
504  
500  
Cyclic Sense/FWU Timing 5  
Sleep and Stop Modes  
74  
Cyclic Sense/FWU Timing 6  
Sleep and Stop Modes  
95.5  
191  
388  
350  
Cyclic Sense/FWU Timing 7  
Sleep and Stop Modes  
Cyclic Sense/FWU Timing 8  
Sleep and Stop Modes  
Cyclic Sense ON Time  
Sleep and Stop Modes Threshold and Condition to be Added  
Cyclic Sense/FWU Timing Accuracy  
Sleep and Stop Modes  
%
t
ACC  
-30  
30  
22  
22  
Delay Between SPI Command and HS1 Turn ON (25)  
Delay Between SPI Command and HS1 Turn OFF (25)  
µs  
µs  
µs  
t
SHSON  
t
SHSOFF  
Delay Between SPI and V2 Turn ON (25)  
Standby Mode  
tS  
V2ON  
9.0  
9.0  
22  
22  
Delay Between SPI and V2 Turn OFF (25)  
Normal Mode  
tS  
µs  
V2OFF  
Notes  
25. Delay starts at falling edge of clock cycle #8 of the SPI command and start of Turn ON or Turn OFF of HS1 or V2.  
33989  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
13  
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