Freescale Semiconductor, Inc.
DIGITAL SWITCHING CHARACTERISTICS FOR GCI MODE
(V
DD
= 5.0 V ± 5%, T = – 40 to + 85°C, C = 150 pF, See Figure 6 and Note 1)
A L
Ref.
No.
42
43
44
45
46
47
48
49
50
51
52
53
Characteristics
Min
Max
Unit
Time Between Successive FSC Pulses
DCL Clock Frequency
Note 2
512
50
50
20
60
—
6176
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DCL Clock Pulse Width High
DCL Clock Pulse Width Low
—
Hold Time of FSC After Falling Edge of DCL
Setup Time of FSC to DCL Falling Edge
Rising Edge of DCL (After Rising Edge of FSC) to Low Impedance and Valid Data of D
—
—
60
60
60
50
—
out
Rising Edge of FSC (While DCL is High) to Low Impedance and Valid Data of D
out
—
Rising Edge of DCL to Valid Data on D
—
out
Second DCL Falling Edge During LSB to High Impedance of D
10
20
—
out
Setup Time of D Before Rising Edge of DCL
in
Hold Time of D After DCL Rising Edge
in
60
NOTES:
1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.
2. In GCI mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words
are accessed during the B2 channel as shown in Figure 6. GCI accesses must occur at a rate of 8 kHz (125 µs interval).
Figure 6. GCI Interface Timing
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