Freescale Semiconductor, Inc.
DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC
(V
DD
= + 5 V ± 5%, V
= 0 V, All Digital Signals Referenced to V , T = – 40 to + 85°C, C = 150 pF, Unless Otherwise Noted)
SS
SS
A
L
Ref.
No.
Characteristics
Min
Typ
Max
Unit
1
Master Clock Frequency for MCLK
—
—
—
—
—
—
—
256
512
—
—
—
—
—
—
—
kHz
1536
1544
2048
2560
4096
1
2
MCLK Duty Cycle for 256 kHz Operation
45
50
50
—
—
50
50
64
50
50
20
80
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
55
—
%
ns
ns
ns
ns
ns
ns
kHz
ns
ns
ns
ns
ns
ns
Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater)
Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater)
Rise Time for All Digital Signals
3
—
4
50
50
—
5
Fall Time for All Digital Signals
6
Setup Time from MCLK Low to FST High
7
Setup Time from FST High to MCLK Low
—
8
Bit Clock Data Rate for BCLKT or BCLKR
4096
—
9
Minimum Pulse Width High for BCLKT or BCLKR
Minimum Pulse Width Low for BCLKT or BCLKR
Hold Time from BCLKT (BCLKR) Low to FST (FSR) High
Setup Time for FST (FSR) High to BCLKT (BCLKR) Low
Setup Time from DR Valid to BCLKR Low
10
11
12
13
14
—
—
—
—
Hold Time from BCLKR Low to DR Invalid
50
—
LONG FRAME SPECIFIC TIMING
15
16
17
18
Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low
Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data
Delay Time from BCLKT High to DT for Valid Chord and Step Bit Data
50
—
—
10
—
—
—
—
—
60
60
60
ns
ns
ns
ns
Delay Time from the Later of the 8th BCLKT Falling Edge, or the Falling Edge
of FST to DT Output High Impedance
19
Minimum Pulse Width Low for FST or FSR
50
—
—
ns
SHORT FRAME SPECIFIC TIMING
20
21
22
23
Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low
Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low
Delay Time from BCLKT High to DT Data Valid
50
50
10
10
—
—
—
—
—
—
60
60
ns
ns
ns
ns
Delay Time from the 8th BCLKT Low to DT Output High Impedance
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