Freescale Semiconductor, Inc.
DIGITAL SWITCHING CHARACTERISTICS FOR IDL MODE
(V
DD
= 5.0 V ± 5%, T = – 40 to + 85°C, C = 150 pF, See Figure 5 and Note 1)
A L
Ref.
No.
31
32
33
34
35
36
37
38
39
40
41
Characteristics
Min
Max
Unit
Time Between Successive IDL Syncs
Note 2
Hold Time of IDL SYNC After Falling Edge of IDL CLK
Setup Time of IDL SYNC Before Falling Edge IDL CLK
IDL Clock Frequency
20
60
256
50
50
20
75
10
10
—
—
—
ns
ns
kHz
ns
ns
ns
ns
ns
ns
ns
4096
—
IDL Clock Pulse Width High
IDL Clock Pulse Width Low
—
Data Valid on IDL RX Before Falling Edge of IDL CLK
Data Valid on IDL RX After Falling Edge of IDL CLK
Falling Edge of IDL CLK to High–Z on IDL TX
Rising Edge of IDL CLK to Low–Z and Data Valid on IDL TX
Rising Edge of IDL CLK to Data Valid on IDL TX
—
—
50
60
50
NOTES:
1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.
2. In IDL mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words
are accessed during the B2 channel as shown in Figure 5. IDL accesses must occur at a rate of 8 kHz (125 µs interval).
Figure 5. IDL Interface Timing
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