Bus Signal Timing
Figure 15 through Figure 17 provide the timing for the external bus write controlled by various GPCM factors.
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B30
B22
B23
B25
B28
WE[0:3]
B29b
B26
OE
B29
B8
B9
D[0:31]
Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)
MPC875/MPC870 Hardware Specifications, Rev. 3.0
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
30
Freescale Semiconductor