Bus Signal Timing
Figure 8 provides the timing for the synchronous input signals.
CLKOUT
B16
B17
TA, BI
B16a
B17a
TEA, KR,
RETRY, CR
B16b
B17
BB, BG, BR
Figure 8. Synchronous Input Signals Timing
Figure 9 provides normal case timing for input data. It also applies to normal read accesses under the control of the
user-programmable machine (UPM) in the memory controller.
CLKOUT
B16
B17
TA
B18
B19
D[0:31]
Figure 9. Input Data Timing in Normal Case
MPC875/MPC870 Hardware Specifications, Rev. 3.0
26
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ Freescale ]
