Bus Signal Timing
Figure 4 provides the control timing diagram.
.
2.0 V
CLKOUT
2.0 V
0.8 V
0.8 V
A
B
2.0 V
2.0 V
0.8 V
Outputs
0.8 V
A
B
2.0 V
0.8 V
2.0 V
0.8 V
Outputs
D
C
2.0 V
2.0 V
0.8 V
Inputs
0.8 V
D
C
2.0 V
0.8 V
2.0 V
0.8 V
Inputs
A
B
C
D
Maximum output delay specification
Minimum output hold time
Minimum input setup time specification
Minimum input hold time specification
Figure 4. Control Timing
Figure 5 provides the timing for the external clock.
CLKOUT
B1
B1
B3
B2
B4
B5
Figure 5. External Clock Timing
MPC875/MPC870 Hardware Specifications, Rev. 3.0
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
24
Freescale Semiconductor
FREESCALE [ Freescale ]
