Bus Signal Timing
Table 10. Bus Operation Timings (continued)
33 MHz 40 MHz 66 MHz
Min Max Min Max Min Max Min Max
80 MHz
Num
Characteristic
Unit
B18 D(0:31) valid to CLKOUT rising edge
6.00
—
—
—
—
6.00
1.00
4.00
2.00
—
—
—
—
6.00
2.00
4.00
2.00
—
—
—
—
6.00
2.00
4.00
2.00
—
—
—
—
ns
ns
ns
ns
ns
ns
(setup time) 4 (MIN = 0.00 × B1 + 6.00)
B19 CLKOUT rising edge to D(0:31) valid (hold 1.00
time) 4 (MIN = 0.00 × B1 + 1.00 5)
B20 D(0:31) valid to CLKOUT falling edge
4.00
2.00
(setup time) 6(MIN = 0.00 × B1 + 4.00)
B21 CLKOUT falling edge to D(0:31) valid
(hold time) 6 (MIN = 0.00 × B1 + 2.00)
B22 CLKOUT rising edge to CS asserted
7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43
GPCM ACS = 00 (MAX = 0.25 × B1 + 6.3)
B22a CLKOUT falling edge to CS asserted
GPCM ACS = 10, TRLX = 0
—
8.00
—
8.00
—
8.00
—
8.00
(MAX = 0.00 × B1 + 8.00)
B22b CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 0
(MAX = 0.25 × B1 + 6.3)
7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43
ns
B22c CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns
B23 CLKOUT rising edge to CS negated
GPCM read access, GPCM write access
ACS = 00, TRLX = 0 & CSNT = 0
(MAX = 0.00 × B1 + 8.00)
2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00
ns
B24 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 0
(MIN = 0.25 × B1 – 2.00)
5.60
13.20
—
—
—
4.30
—
—
1.80
5.60
—
—
1.13
4.25
—
—
—
ns
ns
ns
B24a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11 TRLX = 0
(MIN = 0.50 × B1 – 2.00)
10.50
B25 CLKOUT rising edge to OE,
WE(0:3)/BS_B[0:3] asserted
(MAX = 0.00 × B1 + 9.00)
9.00
9.00
9.00
9.00
B26 CLKOUT rising edge to OE negated
2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00
ns
ns
(MAX = 0.00 × B1 + 9.00)
B27 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 1
(MIN = 1.25 × B1 – 2.00)
35.90
43.50
—
—
29.30
35.50
—
—
16.90
20.70
—
—
13.60
16.75
—
—
B27a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 1
(MIN = 1.50 × B1 – 2.00)
ns
MPC875/MPC870 Hardware Specifications, Rev. 3.0
18
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ Freescale ]
