Bus Signal Timing
Table 9. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part Frequency 66 MHz 80 MHz 133 MHz
Min
Max
Min
Max
Min
Max
Core frequency
Bus frequency
40
20
66.67
33.33
40
20
80
40
40
20
133
66
Table 10 provides the bus operation timing for the MPC875/870 at 33, 40, 66, and 80 MHz.
The timing for the MPC875/870 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay
Table 10. Bus Operation Timings
33 MHz
40 MHz
66 MHz
80 MHz
Num
Characteristic
Unit
Min Max Min Max Min Max Min Max
B1
Bus period (CLKOUT), see Table 8
—
—
—
—
—
—
—
—
ns
ns
B1a EXTCLK to CLKOUT phase skew - If
CLKOUT is an integer multiple of
–2
+2
–2
+2
–2
+2
–2
+2
EXTCLK, then the rising edge of EXTCLK
is aligned with the rising edge of CLKOUT.
For a non-integer multiple of EXTCLK, this
synchronization is lost, and the rising
edges of EXTCLK and CLKOUT have a
continuously varying phase skew.
B1b CLKOUT frequency jitter peak-to-peak
B1c Frequency jitter on EXTCLK
—
—
—
1
0.50
4
—
—
—
1
0.50
4
—
—
—
1
0.50
4
—
—
—
1
0.50
4
ns
%
B1d CLKOUT phase jitter peak-to-peak
ns
for OSCLK ≥ 15 MHz
CLKOUT phase jitter peak-to-peak
for OSCLK < 15 MHz
—
5
—
5
—
5
—
5
ns
ns
ns
B2
B3
CLKOUT pulse width low
(MIN = 0.4 × B1, MAX = 0.6 × B1)
12.1 18.2 10.0 15.0
12.1 18.2 10.0 15.0
6.1
6.1
9.1
9.1
5.0
5.0
7.5
7.5
CLKOUT pulse width high
(MIN = 0.4 × B1, MAX = 0.6 × B1)
B4
B5
B7
CLKOUT rise time
CLKOUT fall time
—
—
4.00
4.00
—
—
—
4.00
4.00
—
—
—
4.00
4.00
—
—
—
4.00
4.00
—
ns
ns
ns
CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31) output hold
(MIN = 0.25 × B1)
7.60
6.30
3.80
3.13
B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,
7.60
7.60
—
—
6.30
6.30
—
—
3.80
3.80
—
—
3.13
3.13
—
—
ns
ns
PTR output hold (MIN = 0.25 × B1)
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),
VF(0:2) IWP(0:2), LWP(0:1), STS output
hold (MIN = 0.25 × B1)
MPC875/MPC870 Hardware Specifications, Rev. 3.0
16
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ Freescale ]
