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DSPA56371 参数 Datasheet PDF下载

DSPA56371图片预览
型号: DSPA56371
PDF下载: 下载PDF文件 查看货源
内容描述: 该DSP56371是5.0伏兼容的输入和输出的高密度CMOS器件。 [The DSP56371 is a high density CMOS device with 5.0-volt compatible inputs and outputs.]
分类和应用:
文件页数/大小: 124 页 / 1701 K
品牌: FREESCALE [ Freescale ]
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Signal/Connection Descriptions  
Table 7. Serial Host Interface Signals (Continued)  
State  
Signal  
Name  
Signal  
Type  
during  
Reset  
Signal Description  
Input  
Input  
Tri-stated SPI Slave Select—This signal is an active low Schmitt-trigger input when  
configured for the SPI mode. When configured for the SPI Slave mode, this  
signal is used to enable the SPI slave for transfer. When configured for the SPI  
master mode, this signal should be kept deasserted (pulled high). If it is  
asserted while configured as SPI master, a bus error condition is flagged. If SS  
is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in  
the high-impedance state.  
SS  
HA2  
I2C Slave Address 2—This signal uses a Schmitt-trigger input when  
configured for the I2C mode. When configured for the I2C Slave mode, the HA2  
signal is used to form the slave device address. HA2 is ignored in the I2C  
master mode.  
This signal is tri-stated during hardware, software and individual reset. Thus,  
there is no need for an external pull-up in this state.  
Internal Pull up resistor.  
This input is 5 V tolerant.  
Input or  
Output  
Tri-stated Host Request—This signal is an active low Schmitt-trigger input when  
configured for the master mode but an active low output when configured for the  
slave mode.  
HREQ  
When configured for the slave mode, HREQ is asserted to indicate that the SHI  
is ready for the next data word transfer and deasserted at the first clock pulse of  
the new data word transfer. When configured for the master mode, HREQ is an  
input. When asserted by the external slave device, it will trigger the start of the  
data word transfer by the master. After finishing the data word transfer, the  
master will await the next assertion of HREQ to proceed to the next transfer.  
This signal is tri-stated during hardware, software, personal reset, or when the  
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for an external  
pull-up in this state.  
Internal Pull up resistor.  
This input is 5 V tolerant.  
16  
DSP56371 Technical Data  
Freescale Semiconductor  
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