Specifications
501
502
502
V
M
V
V
M
TCK
(Input)
IH
V
IL
503
503
Figure 2-46. Test Clock Input Timing Diagram
V
TCK
(Input)
IH
V
IL
504
505
Data
Inputs
Input Data Valid
506
507
506
Data
Outputs
Output Data Valid
Data
Outputs
Data
Outputs
Output Data Valid
Figure 2-47. Boundary Scan (JTAG) Timing Diagram
V
IH
TCK
(Input)
V
IL
509
508
Input Data Valid
TDI
TMS
(Input)
510
TDO
(Output)
Output Data Valid
511
TDO
(Output)
510
TDO
(Output)
Output Data Valid
Figure 2-48. Test Access Port Timing Diagram
DSP56301 Technical Data, Rev. 10
2-50
Freescale Semiconductor