90
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Low Speed Serial Interface Timing Specifications
The low speed serial interface timing is shown in Figure 21 and described in Table 46.
Figure 21 Low Speed Serial Interface Timing Diagram
Cycle 2
Cycle 3
SICL
T
slc
T
T
T
T
T
slb
slss
slhs
slhd
slsd
T
slst
SIDA
Table 46 Low Speed Serial Interface Timing Description
SYMBOL PARAMETER
MIN
2500
600
600
250
0.0
MAX
UNIT
ns
Tslc
SICL Cycle Time
Tslss
Tslhs
Tslsd
Tslhd
Tslst
Tslb
Set-up Time for Repeated START Condition
Hold Time START Condition
Data Set-up Time
ns
ns
ns
Data Hold Time
ns
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Capacitive load for each line of the bus
600
1250
ns
ns
Cmax
400
pF
C3EN
FREESCALE [ Freescale ]
