Freescale Semiconductor, Inc.
Port B4, B2, B1, AVEC
This signal group functions as three bits of parallel I/O and the autovector input. AVEC
requests an automatic vector during an interrupt acknowledge cycle.
2.6 INTERRUPT REQUEST LEVEL (IRQ7, IRQ6, IRQ5, IRQ3)
These pins can be programmed to be either prioritized interrupt request lines or port B
parallel I/O.
IRQ7, IRQ6, IRQ5, IRQ3
IRQ7, the highest priority, is nonmaskable. IRQ6–IRQ1 are internally maskable
interrupts. Refer to Section 5 CPU32 for more information on interrupt request lines.
Port B7, B6, B5, B3
These pins can be used as port B parallel I/O. Refer to Section 4 System Integration
Module for more information on parallel I/O signals.
2.7 BUS CONTROL SIGNALS
These signals control the bus transfer operations of the MC68340. Refer to Section 3
Bus Operation for more information on these signals.
2.7.1 Data and Size Acknowledge (DSACK1, DSACK0)
These two active-low input signals allow asynchronous data transfers and dynamic data
bus sizing between the MC68340 and external devices as listed in Table 2-3. During bus
cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol.
During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the
data. During a write cycle, this indicates that the external device has successfully stored
the data and that the cycle may terminate.
Table 2-3. DSACK≈ Encoding
DSACK
1
DSACK
0
Result
1
1
0
0
1
0
1
0
Insert Wait States in Current Bus Cycle
Complete Cycle—Data Bus Port Size Is 8 Bits
Complete Cycle—Data Bus Port Size Is 16 Bits
Reserved—Defaults to 16-Bit Port Size Can Be
Used for 32-Bit DMA Cycles
2.7.2 Address Strobe (AS)
AS is an output timing signal that indicates the validity of both an address on the address
bus and many control signals. AS is asserted approximately one-half clock cycle after the
beginning of a bus cycle.
2- 6
MC68340 USER’S MANUAL
MOTOROLA
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