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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Table 2-1. Signal Index (Continued)  
Input/  
Signal Name  
Mnemonic  
Function  
Output  
Clock Mode Select/  
Port B0  
MODCK  
Selects the source of the internal system clock upon reset  
or becomes a parallel I/O port  
In/I/O  
Instruction Fetch/  
Development Serial In  
IFETCH/DSI  
IPIPE/DSO  
Indicates when the CPU32 is performing an instruction  
word prefetch and when the instruction pipeline has been  
flushed or provides background debug mode serial in  
Out/In  
Instruction Pipe/  
Development Serial Out  
Used to track movement of words through the instruction  
pipeline or provides background debug mode serial out  
Out/Out  
In/—  
Breakpoint/Development  
Serial Clock  
BKPT/DSCLK Signals a hardware breakpoint to the CPU32 or provides  
background debug mode serial clock  
Freeze  
FREEZE  
Indicates that the CPU32 has entered background debug  
mode  
Out  
Transmit Data  
Clear-to-Send  
TxDA, TxDB  
Transmitter serial data output from the serial module  
Out  
In  
CTSA, CTSB Serial module clear-to-send inputs  
Request-to-Send/  
OP1, OP0  
RTSB, RTSA Channel request-to-send outputs or discrete outputs  
Out/Out  
Serial Crystal Oscillator  
X1, X2  
Connections for an external crystal to the serial module  
internal oscillator circuit  
Serial Clock  
SCLK  
External serial module clock input  
In  
Transmitter Ready/OP6  
TRDYA  
Indicates transmit buffer has a character or becomes a  
parallel output  
Out/Out  
Receiver Ready/  
FIFO Full/OP4  
RRDYA  
Indicates receive buffer has a character, the receiver  
FIFO buffer is full or becomes a parallel output  
Out/Out/Out  
In  
DMA Request  
DRE  
Input that starts a DMA process  
Q2, DREQ1  
DMA Acknowledge  
DMA Done  
DACK2,  
DACK1  
Output that signals an access during DMA  
Bi-directional signal that indicates the last transfer  
Counter enable input to timer  
Out  
I/O  
In  
DONE2,  
DONE1  
Timer Gate  
TGATE2,  
TGATE1  
Timer Input  
TIN2, TIN1  
Time reference input to timer  
Output waveform from timer  
In  
Timer Output  
TOUT2,  
TOUT1  
Out  
Test Clock  
TCK  
TMS  
TDI  
Provides a clock for IEEE 1149.1 test logic  
Controls test mode operations  
In  
In  
Test Mode Select  
Test Data In  
Shifts in instructions and test data  
Shifts out instructions and test data  
In  
Test Data Out  
Synchronizer Power  
TDO  
Out  
V
Quiet power supply to VCO; also used to control  
synthesizer mode after reset.  
CCSYN  
System Power Supply  
and Ground  
V
CC  
, GND  
Power supply and ground to the MC68340  
MOTOROLA  
MC68340 USER’S MANUAL  
2- 3  
For More Information On This Product,  
Go to: www.freescale.com  
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