Freescale Semiconductor, Inc.
RxRDYB—Channel B Receiver Ready or FIFO full
1 = Enable interrupt
0 = Disable interrupt
TxRDYB—Channel B Transmitter Ready
1 = Enable interrupt
0 = Disable interrupt
Bit 3—Reserved
DBA—Delta Break A
1 = Enable interrupt
0 = Disable interrupt
RxRDYA—Channel A Receiver Ready or FIFO full
1 = Enable interrupt
0 = Disable interrupt
TxRDYA—Channel A Transmitter Ready
1 = Enable interrupt
0 = Disable interrupt
7.4.1.14 INPUT PORT (IP). The IP register shows the current state of the CTS≈ inputs.
This register can only be read when the serial module is enabled (i.e., the STP bit in the
MCR is cleared).
IP
$71D
0
7
0
6
0
5
0
4
0
3
0
2
0
1
CTSB
CTSA
RESET:
0
0
0
0
0
0
U
U
Read Only
Supervisor/User
CTSB, CTSA—Current State
1 = The current state of the respective CTS≈ input is negated.
0 = The current state of the respective CTS≈ input is asserted.
The information contained in these bits is latched and reflects the state of the input pins
at the time that the IP is read.
NOTE
These bits have the same function and value of the IPCR bits 1
and 0.
MOTOROLA
MC68340 USER’S MANUAL
7- 35
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