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• Select the direction of transfer if in single-address mode (ECO bit), or select which
device generates requests if in dual-address mode.
6.9.1.1 DMA CHANNEL OPERATION IN SINGLE-ADDRESS MODE. The following steps
are required to begin a DMA transfer in single-address mode.
Channel Control Register (CCR)
• Write a zero to the start bit (STR) to prevent the channel from starting the transfer
prematurely.
• Select the amount by which to increment the source address for a read cycle (SAPI
bit) or the destination address for a write cycle (DAPI bit).
• Define the transfer size by selecting the source size for a read cycle (SSIZE field) or
by selecting the destination size for a write cycle (DSIZE field).
• Select external burst request mode or external cycle steal request mode (REQ field).
• Set the S/D bit for signal-address transfer.
Channel Status Register (CSR)
• Clear the CSR by writing $7C into it. The DMA cannot be started until the DONE, BES,
BED, CONF, and BRKP bits are cleared.
Function Code Register (FCR)
• Encode the source function code for a read cycle or the destination function code for a
write cycle.
Address Register (SAR or DAR)
• Write the source address for a read cycle or the destination address for a write cycle.
Byte Transfer Counter (BTC)
• Encode the number of bytes to be transferred.
Channel Control Register (CCR)
• Write a one to the start bit (STR) to allow the transfer to begin.
6.9.1.2 DMA CHANNEL OPERATION IN DUAL-ADDRESS MODE. The following steps
are required to begin a DMA transfer in dual-address mode.
Channel Control Register (CCR)
• Write a zero to the start bit (STR) to prevent the channel from starting the transfer
prematurely.
• Select the amount by which to increment the source and destination addresses (SAPI
and DAPI bits).
• Select the source and destination sizes (SSIZE and DSIZE fields).
• Select internal request, external burst request mode, or external cycle steal request
mode (REQ field).
MOTOROLA
MC68340 USER’S MANUAL
6- 37
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