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address. In the single-address mode with the source (read) device requesting mode of
operation, this register is not used.
The manner in which the SAR and DAR change after each cycle depends upon the values
in the CCR SSIZE and DSIZE fields and SAPI and DAPI bits, and the starting address in
the SAR and DAR. If programmed to increment, the increment value is 1, 2, or 4 for byte,
word, or long-word operands, respectively. If the address register is programmed to
remain unchanged (no count), the register is not incremented after the operand transfer.
The SAR and DAR are incremented if a bus error terminates the transfer. Therefore,
either the SAR or the DAR contain the next address after the one that caused the bus
error.
The BTC must be loaded with the number of byte transfers that are to occur. This register
is decremented by 1, 2, or 4 at the end of each transfer. The FCR must be loaded with the
source and destination function codes. Although these function codes may not be used in
the address decode for the memory or peripheral, they are provided if needed. The CSR
must be cleared for channel startup.
Once the channel has been initialized, it is started by writing a one to the STR bit in the
CCR. Programming the channel for internal request causes the channel to request the bus
and start transferring data immediately. If the channel is programmed for external request,
DREQ≈ must be asserted before the channel requests the bus. The DREQ≈ input is
ignored until the channel is started, since the channel does not recognize transfer
requests until it is active.
If any fields in the CCR are modified while the channel is active, that change is effective
immediately. To avoid any problems with changing the setup for the DMA channel, a zero
should be written to the STR bit in the CCR to halt the DMA channel at the end of the
current bus cycle.
6.6.2 Data Transfers
Each operand transfer requires from one to five bus cycles to complete. Once a bus
request is recognized and the operand transfer begins, both the source (read) cycle
and/or the destination (write) cycle occur before a new bus request may be honored, even
if the new bus request is of higher priority.
6.6.2.1 INTERNAL REQUEST TRANSFERS. Internally generated request transfers are
accessed as two-clock bus cycles. (The IMB can access on-chip peripherals in two
clocks.) The percentage of bus bandwidth utilization can be limited for internal request
transfers.
6.6.2.2 EXTERNAL REQUEST TRANSFERS. In single-address mode, only one bus cycle
is run for each request. Since the operand size must be equal to the device port size in
single-address mode, the number of normally terminated bus cycles executed during a
transfer operation is always equal to the value programmed into the corresponding size
field of the CCR. The sequencing of the address bus follows the programming of the CCR
and address register (SAR or DAR) for the channel.
MOTOROLA
MC68340 USER’S MANUAL
6- 19
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