Freescale Semiconductor, Inc.
5.7.3.2 CALCULATE EFFECTIVE ADDRESS. The calculate EA table indicates the
number of clock periods needed for the processor to calculate a specified EA. The timing
is equivalent to fetch EA except there is no read cycle. The tail and cycle time are reduced
by the amount of time the read would occupy. The total number of clock cycles is outside
the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock
cycle number. All timing data assumes two-clock reads and writes.
Instruction
Head
–
Tail
–
–
0
0
0
1
1
3
0
0
1
3
0
0
0
1
3
0
1
0
1
Cycles
0(0/0/0)
0(0/0/0)
2(0/0/0)
2(0/0/0)
2(0/0/0)
3(0/1/0)
3(0/1/0)
5(0/2/0)
6(0/1/0)
4(0/1/0)
5(0/2/0)
7(0/3/0)
4(0/1/0)
6(0/1/0)
6(0/1/0)
5(0/2/0)
7(0/3/0)
6(0/2/0)
7(0/3/0)
6(0/2/0)
7(0/3/0)
Notes
–
Dn
An
–
–
(An)
(An)+
−(An)
1
–
1
–
2
–
(d ,An) or (d ,PC)
16
16
1
1,3
1
(xxx).W
1
(xxx).L
1
1
(d ,An,Xn.Sz × Sc) or (d ,PC,Xn.Sz × Sc)
8
8
4
2,3,4
4
(0) (All Suppressed)
2
(d
(d
)
)
16
32
1
1,4
1,4
4
1
(An)
1
(Xm.Sz × Sc)
4
2,4
2,4
1,3,4
1,3,4
3,4
1,3,4
2,3,4
1,2,3,4
(An,Xm.Sz × Sc)
4
(d ,An) or (d ,PC)
16
16
1
(d ,An) or (d ,PC)
32
32
1
(d ,An,Xm) or (d ,PC,Xm)
16
16
2
(d ,An,Xm) or (d ,PC,Xm)
32
32
1
(d ,An,Xm.Sz × Sc) or (d ,PC,Xm.Sz × Sc)
16
16
2
(d ,An,Xm.Sz × Sc) or (d ,PC,Xm.Sz × Sc)
32
32
1
X = There is one bus cycle for byte and word operands and two bus cycles for long operands.
For long bus cycles, add two clocks to the tail and to the number of cycles.
NOTES:
1. Replacement fetches overlap the head of the operation by the amount specified in the tail.
2. Size and scale of the index register do not affect execution time.
3. The PC may be substituted for the base address register An.
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the
head until the head reaches zero, at which time additional clocks must be added to both the tail
and cycle counts.
5-100
MC68340 USER’S MANUAL
MOTOROLA
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