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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Because of the stipulation that each instruction must prefetch to replace itself, the concept  
of negative tails has been introduced to account for these free clocks on the bus.  
On a two-clock bus, it is not necessary to adjust instruction timing to account for the  
potential extra prefetch. The cycle times of the microsequencer and bus are matched, and  
no additional benefit or penalty is obtained. In the instruction execution time equations, a  
zero should be used instead of a negative number.  
Negative tails are used to adjust for slower fetches on slower buses. Normally, increasing  
the length of prefetch bus cycles directly affects the cycle count and tail values found in  
the tables.  
In the following equations, negative tail values are used to negate the effects of a slower  
bus. The equations are generalized, however, so that they may be used on any speed bus  
with any tail value.  
NEW_TAIL = OLD_TAIL + (NEW_CLOCK – 2)  
IF ((NEW_CLOCK – 4) >0) THEN  
NEW_CYCLE = OLD_CYCLE + (NEW_CLOCK -2) + (NEW_CLOCK – 4)  
ELSE  
NEW_CYCLE = OLD_CYCLE + (NEW _CLOCK – 2)  
where:  
NEW_TAIL/NEW_CYCLE is the adjusted tail/cycle at the slower speed  
OLD_TAIL/OLD_CYCLE is the value listed in the instruction timing tables  
NEW_CLOCK is the number of clocks per cycle at the slower speed  
Note that many instructions listed as having negative tails are change-of-flow instructions  
and that the bus speed used in the calculation is that of the new instruction stream.  
5.7.2 Instruction Stream Timing Examples  
The following programming examples provide a detailed examination of timing effects. In  
all examples, the memory access is from external synchronous memory, the bus is idle,  
and the instruction pipeline is full at the start.  
5.7.2.1 TIMING EXAMPLE 1—EXECUTION OVERLAP. Figure 5-33 illustrates execution  
overlap caused by the bus controller's completion of bus cycles while the sequencer is  
calculating the next EA. One clock is saved between instructions since that is the  
minimum time of the individual head and tail numbers.  
Instructions  
MOVE.W  
ADDQ.W  
CLR.W  
A1, (A0) +  
#1, (A0)  
$30 (A1)  
5- 94  
MC68340 USER’S MANUAL  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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