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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
analyzed. To derive the actual instruction execution times for an instruction sequence, the  
instruction times listed in the tables must be adjusted to account for overlap.  
The formula for this calculation is as follows:  
C1 min (T , H ) + C min (T , H ) + C min (T , H ) + .. .. .  
1
2
2
2
3
3
3
4
where:  
C is the number of cycles listed for instruction N  
N
T is the tail time for instruction N  
N
H is the head time for instruction N  
N
min (T , H ) is the minimum of parameters T and H  
M
N
M
N
The number of cycles for the instruction (C ) can include one or two EA calculations in  
N
addition to the raw number in the cycles column. In these cases, calculate overall  
instruction time as if it were for multiple instructions, using the following equation:  
CEA min (T , H ) + C  
EA OP  
OP  
where:  
CEA is the instruction’s EA time  
C
is the instruction’s operation time  
OP  
EA  
T
is the EA’s tail time  
H
is the instruction operation’s head time  
OP  
min (T , H ) is the minimum of parameters T and H  
M
N
M
N
The overall head for the instruction is the head for the EA, and the overall tail for the  
instruction is the tail for the operation. Therefore, the actual equation for execution time  
becomes:  
C
min (T  
, H  
) + CEA min (T  
, H  
) + C  
min (T  
, H  
) + . . .  
OP1  
OP1  
EA2  
2
EA2  
OP2  
OP2  
OP2  
EA3  
Every instruction must prefetch to replace itself in the instruction pipe. Usually, these  
prefetches occur during or after an instruction. A prefetch is permitted to begin in the first  
clock of any indexed EA mode operation.  
Additionally, a prefetch for an instruction is permitted to begin two clocks before the end of  
an instruction provided the bus is not being used. If the bus is being used, then the  
prefetch occurs at the next available time when the bus would otherwise be idle.  
5.7.1.7 EFFECTS OF NEGATIVE TAILS. When the CPU32 changes instruction flow, the  
instruction decode pipeline must begin refilling before instruction execution can resume.  
Refilling forces a two-clock idle period at the end of the change-of-flow instruction. This  
idle period can be used to prefetch an additional word on the new instruction path.  
MOTOROLA  
MC68340 USER’S MANUAL  
5- 93  
For More Information On This Product,  
Go to: www.freescale.com  
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