Switching specifications
Table 5. Control timing (continued)
Num
C
Rating
IRQ pulse width
Symbol
Min
Typical1
Max
Unit
7
D
Asynchronous
path2
tILIH
100
—
—
ns
D
D
Synchronous path
tIHIL
tILIH
1.5 × tcyc
100
—
—
—
—
ns
ns
8
9
Keyboard interrupt pulse
width
Asynchronous
path2
D
C
C
Synchronous path
—
tIHIL
tRise
tFall
1.5 × tcyc
—
10.2
9.5
—
—
—
ns
ns
ns
Port rise and fall time -
Normal drive strength
(HDRVE_PTXx = 0) (load
= 50 pF)
—
—
C
C
Port rise and fall time -
Extreme high drive
—
tRise
tFall
—
—
5.4
4.6
—
—
ns
ns
strength (HDRVE_PTXx =
1) (load = 50 pF)4
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after
VDD rises above VLVD
.
4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.
textrst
RESET PIN
Figure 5. Reset timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 6. IRQ/KBIPx timing
5.2.2 Debug trace timing specifications
Table 6. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
MHz
ns
tcyc
twl
twh
tr
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
2
2
—
—
3
ns
—
—
ns
tf
3
ns
Table continues on the next page...
MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.
14
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
