Freescale Semiconductor, Inc.
Operating Modes
When selected as inputs, these pins can be configured to be high
impedance or pulled up.
ECS — Emulation Chip Select of selected program space
When this signal is active low it indicates that the program space is
accessed. This also applies to test mode program space. An access
is made if an address is in the program space window and either the
Flash or external memory is accessed. The ECS timing is E clock high
and can be stretched when accessing external memory depending on
the EXTR0 and EXTR1 bits in the MISC register. The ECS signal is
only active when the EMK bit is set.
PIX[2:0] — The content of the PPAGE register emulated externally.
This content indicates which Flash module register space is in the
memory map and which 16K byte Flash memory is in the program
space. In special mode and with ROMTST bit set, the content of the
Page Index register indicates which 32K byte Flash array is in the test
program space.
DDRK — Port K Data Direction Register
$00FD
Bit 7
DDK7
0
6
0
0
5
0
0
4
0
0
3
DDK3
0
2
DDK2
0
1
DDK1
0
Bit 0
DDK0
0
RESET:
Read and write: anytime.
This register determines the primary direction for each port K pin
configured as general-purpose I/O.
0 = Associated pin is a high-impedance input.
1 = Associated pin is an output.
This register is not in the map in peripheral or expanded modes when the
EMK control bit is set.
Technical Data
MC68HC912DG128 — Rev 3.0
Operating Modes
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