Freescale Semiconductor, Inc.
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Bit 7
BKEN1
0
6
BKEN0
0
5
BKPM
0
4
0
0
3
BK1ALE
0
2
BK0ALE
0
1
0
0
Bit 0
0
0
RESET:
BRKCT0 — Breakpoint Control Register 0
$0020
Read and write anytime.
This register is used to control the breakpoint logic.
BKEN1, BKEN0 — Breakpoint Mode Enable
Table 18-9. Breakpoint Mode Control
BKEN1 BKEN0
Mode Selected
Breakpoints Off
BRKAH/L Usage BRKDH/L Usage R/W
Range
0
0
1
1
0
1
0
1
—
—
—
—
SWI — Dual Address Mode
BDM — Full Breakpoint Mode
BDM — Dual Address Mode
Address Match
Address Match
Address Match
Address Match
Data Match
Address Match
No
Yes
Yes
Yes
Yes
Yes
BKPM — Break on Program Addresses
This bit controls whether the breakpoint will cause a break on a match
(next instruction boundary) or on a match that will be an executable
opcode. Data and non-executed opcodes cannot cause a break if this
bit is set. This bit has no meaning in SWI dual address mode. The
SWI mode only performs program breakpoints.
0 = On match, break at the next instruction boundary
1 = On match, break if the match is an instruction that will be
executed. This uses tagging as its breakpoint mechanism.
BK1ALE — Breakpoint 1 Range Control
Only valid in dual address mode.
0 = BRKDL will not be used to compare to the address bus.
1 = BRKDL will be used to compare to the address bus.
BK0ALE — Breakpoint 0 Range Control
Valid in all modes.
0 = BRKAL will not be used to compare to the address bus.
1 = BRKAL will be used to compare to the address bus.
Technical Data
MC68HC912DG128 — Rev 3.0
Development Support
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