Freescale Semiconductor, Inc.
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BK1RWE — R/W Compare Enable
Enables the comparison of the R/W signal to further specify what
causes a match. This bit is NOT useful in program breakpoints or in
full breakpoint mode. This bit is used in conjunction with a second
address in dual address mode when BKDBE=1.
0 = R/W is not used in comparisons
1 = R/W is used in comparisons
BK1RW — R/W Compare Value
When BK1RWE = 1, this bit determines the type of bus cycle to
match.
0 = A write cycle will be matched
1 = A read cycle will be matched
BK0RWE — R/W Compare Enable
Enables the comparison of the R/W signal to further specify what
causes a match. This bit is not useful in program breakpoints.
0 = R/W is not used in the comparisons
1 = R/W is used in comparisons
BK0RW — R/W Compare Value
When BK0RWE = 1, this bit determines the type of bus cycle to match
on.
0 = Write cycle will be matched
1 = Read cycle will be matched
Table 18-11. Breakpoint Read/Write Control
BK1RWE BK1RW BK0RWE BK0RW
Read/Write Selected
R/W is don’t care for full mode or dual mode BKP0
R/W is write for full mode or dual mode BKP0
R/W is read for full mode or dual mode BKP0
R/W is don’t care for dual mode BKP1
R/W is write for dual mode BKP1
–
–
–
0
1
1
–
–
–
X
0
1
0
1
1
–
–
–
X
0
1
–
–
–
R/W is read for dual mode BKP1
Technical Data
MC68HC912DG128 — Rev 3.0
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