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68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
I/O Ports with Key Wake-up  
10.4 Key Wake-Up Input Filter  
The KWU input signals are filtered by a digital filter which is active only  
during STOP mode. The purpose of the filter is to prevent single pulses  
shorter than a specified value from waking the part from STOP.  
The filter is composed of an internal oscillator and a majority voting logic.  
The filter oscillator starts oscillation by detecting a triggering edge on an  
input if the corresponding interrupt enable bit is set. The majority voting  
logic takes three samples of an asserted input pin at each filter oscillator  
period and if two samples are taken at the triggering level, the filter  
recognizes a valid triggering level and sets the corresponding interrupt  
flag. In this way, the majority voting logic rejects the short non-triggering  
state between two incoming triggering pulses. As the filter is shared with  
all KWU inputs, the filter considers any pulse coming from any input pin  
for which the corresponding interrupt enable bit is set.  
The timing specification is given for a single pulse. The time interval  
between the triggering edges of two following pulses should be greater  
than the tKWSP in order to be considered as a single pulse by the filter. If  
this time interval is shorter than tKWSP, the majority voting logic may treat  
the two consecutive pulses as a single valid pulse.  
The filter is shared by all the KWU pins. Hence any valid triggering level  
on any KWU pin is seen by the filter. The timing specification applies to  
the input of the filter.  
Technical Data  
MC68HC912DG128 — Rev 3.0  
I/O Ports with Key Wake-up  
For More Information On This Product,  
Go to: www.freescale.com  
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