Freescale Semiconductor, Inc.
Flash Memory
7.10 Erasing the Flash EEPROM
The following sequence demonstrates the recommended procedure for
erasing any of the Flash EEPROM. The VFP pin voltage must be at the
proper level prior to executing step 4 the first time.
1. Turn on VFP (apply program/erase voltage to the VFP pin).
2. Set the PPAGE register to point to the 32K Flash array to be
erased. Set the LAT bit and ERAS bit to configure the Flash
EEPROM for erasing.
3. Write to any valid address in the 32K Flash array. This allows the
erase voltage to be turned on; the data written and the address
written are not important. The boot block will be erased only if the
control bit BOOTP is negated.
4. Apply erase voltage by setting ENPE.
5. Delay for a single erase pulse (tEPULSE).
6. Remove erase voltage by clearing ENPE.
7. Delay while high voltage is turning off (tVERASE).
8. Read the entire array to ensure that the Flash EEPROM is erased.
9. If all of the Flash EEPROM locations are not erased, repeat steps
4 through 7 until either the remaining locations are erased, or until
the maximum erase pulses have been applied (nEP)
10. If all of the Flash EEPROM locations are erased, repeat the same
number of pulses as required to erase the array. This provides
100% erase margin.
11. Read the entire array to ensure that the Flash EEPROM is erased.
12. Clear LAT.
13. Turn off VFP (reduce voltage on VFP pin to VDD).
The flowchart in Figure 7-2 demonstrates the recommended erase
sequence.
Technical Data
MC68HC912DG128 — Rev 3.0
Flash Memory
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